As the scale of devices in ICs has become smaller, the devices have become more vulnerable to electrostatic discharge. Hence, ESD has been one of the most important reliability issues for IC products and must be taken into consideration in the design phase of all ICs. Industrial standards require input/output (I/O) pins to pass ESD tests of 2000 volts of human body mode (HBM) and 200 volts of machine mode (MM). Generally, ESD protection devices are placed near I/O pads, protecting not only I/O circuit but also core circuits from ESD damage.
A conventional high-voltage tolerant I/O circuit is usually implemented by a stacked nMOS transistor. However, the stacked nMOS transistor configuration usually has a lower ESD level and slow turn-on speed of the parasitic lateral npn device, as compared with the single nMOS. Such disadvantages result from the longer base width of the lateral npn bipolar junction transistor (BJT) device in the stacked nMOS device. Therefore, an additional ESD protection design must be provided to protect the stacked nMOS. However, most of conventional designs need extra area for additional ESD protection circuit or ESD protection circuit, which are not impracticable in mass production.